1. Field of the Invention
This invention relates generally to testing systems of integrated circuits (ICs) and in particular to testing of ICs for electrostatic discharge (ESD) sensitivity based on the industry standard Human Body Model (HBM) test pulse waveform.
2. Description of the Related Art
Testing of ICs for ESD sensitivity involves simulating a discharge from a human hand. Standard stress pulses are specified by various standards bodies in their specifications, including Military Specifications {MIL-883E-Method 3015.7}, JEDEC/Electronics Industries Association {EIA/JESD 22-114C}, Electrostatic Discharge Assoc. {ESDA/ANSI STM 5.1-HBM, 2001}, Automotive Electronics Council {AEC-Q101-001, Rev-B, July 2000}, and Japan Electronics and Information Technology Industries Association {EIAJ ED4701/300 Method 304}. All these industry specifications describe a common typical pulse generation circuit for human body model (HBM) testing which is well known to those familiar with the HBM testing art.
The industry standards describe a typical pulse generation circuit as being an energy storage capacitor that is charged to a high voltage and then discharged into the DUT through a fixed resistance. A relay switch controls the charging and discharging of this energy storage capacitor. The non-ideal characteristics of this relay are the source of several undesired anomalies in the HBM pulse. What is needed is an HBM pulse generating circuit whereby these non-ideal characteristics of the relay switch are mitigated or have no effect on the pulse produced.
More specifically, recent technological advances in integrated circuit designs have produced ICs that are more sensitive to small anomalies in the pulses commonly produced by these typical pulse generation circuits as documented in several research papers in 2004 and 2005. The non-ideal pulse properties include: a) a pulse coupled by the relay switch during charging of the storage capacitor; b) pre-pulse ringing from the relays coil when activated; c) a voltage ramp before pulse front edge due to relay switch motion; d) secondary or spurious after-pulses; e) a current leakage post-pulse; and f) relay switching noise. These pulse anomalies can produce stresses and cause IC damage, resulting in performance degradation or failure. For some ICs, such tester anomaly damage may be confused with ESD damage and therefore impair the proper ESD testing of ICs. Industry standards are being updated to include limits on these pulse anomalies, e.g., JEDEC EIA/JESD 22-114C. Therefore, a need exits in the art of ESD test systems for a tester that eliminates or reduces to negligible levels undesired anomalies in the test pulses being produced.
When stress pulses are applied to an IC, a residual amount of electrical charge that was forced through the IC may remain stored inside the IC. Such remaining charge may adversely affect subsequent testing. The industry standards often specify the addition of a second relay switch to a pulser circuit to provide an electrical path for removing residual charge after each stress pulse application. Such a second relay switch can produce additional unwanted stress to the IC since operation of the switch may cause a sudden removal of the stored charge, resulting in a high current pulse. Prior art ESD testers have added current limiting resistors to address this problem. A need exists to prevent discharge relay inducted stress while not distorting the HBM test pulse.
FIG. 1 is a schematic diagram of an exemplary prior art HBM electrostatic discharge test device 10 for testing the response of a device under test (DUT). A relay switch S1 operates to first couple a high voltage source HV1 to an energy storage capacitor C1 and then, once capacitor C1 is charged, switch S1 decouples it from HV1 and couples C1 to the DUT through a series connected resistor R1. The power supply HV1 charges the capacitor C1 to the desired high voltage, Vo, when the relay switch S1 is in the deactivated state, as illustrated. The power supply HV1 may have a high impedance output (1 MΩ or more) or may include a series resistor to limit the charging rate of C1. When switch S1 is activated, capacitor C1 is connected to the series connection of R1 and terminal A of the DUT and the HBM test pulse is generated. The peak current of the HBM pulse applied to the DUT is approximately Vo/(R1+RDUT), where Vo is the initial voltage and R1 is approximately 1500 ohms. RDUT is the effective resistance of the DUT between terminals A and B. The current pulse portion of the HBM pulse exponentially decays to zero with a time constant of C1·(R1+RDUT). After the HBM pulse has fully decayed to zero, switch S1 is deactivated and a relay switch S2, connected across the DUT between terminals A and B, is activated. Switch S2 provides a discharge path for any residual charge that may be stored by the DUT. It is common practice to add a resistor R2, having a resistance of between 10K and 10M ohms, in series with S2 to limit the DUT discharge current as required by some industry standards. When switch S1 is returned to its initial deactivated position, capacitor C1 will again be recharged by HV1. Switch S2 is opened at some point before the next HBM test pulse is generated.
Switch S1 is typically implemented with mercury wetted contacts held in a glass envelope containing a high-pressure inert gas and activated by a coil of wire surrounding the envelope. When switch S1 is activated by applying current to the relay coil, the armature that provides the “common” relay contact moves from the “normally closed” relay contact 12 to the “normally open” contact 14 under the electromagnetic force from the coil. The anomalies associated with the operation of this relay include those specified as a)-e) above. One or more other relay switches are often also used in prior art HBM test devices to conduct the HBM pulse to the IC (DUT) and/or to provide one or more paths to ground to complete the pulse conduction path, and these additional relay switches can also induce noise when they switch.
FIG. 2 is a waveform diagram that illustrates exemplary anomalies generated by prior art HBM pulse test devices. With regard to anomaly a), a spurious pulse may be generated when the aforementioned relay switch connects the high voltage supply to the storage capacitor to charge this capacitor, and such a pulse is shown at A in FIG. 2. While the voltage across capacitor C1 increases from zero to the level of the high voltage supply voltage, the small parasitic capacitance formed by the relay contacts will couple this voltage ramp to the DUT. Because the high voltage supply typically provides thousands of volts, only a few picofarads of parasitic relay capacitance can produce voltages at the DUT that can exceed the DUT's normal operating voltage. What is needed is a circuit that removes or eliminates charging pulse anomalies that are generated in this fashion.
Pre-pulse ringing noise, anomaly b), is shown at B in FIG. 2, and is due to coupling of an electric field from the relay coil to the relay's internal metal contacts when voltage is applied to the relay coil. This pre-pulse noise occurs when the relay coil current begins to flow through the relay coil before the movable metal reed armature of the relay switch has time to move. Pre-pulse ringing noise is typically an oscillating voltage pulse that precedes the HBM pulse by the amount of time required for the relay's contacts to move from their deactivated position to where the relay switch conducts the HBM pulse current from capacitor C1 to the DUT. This time duration is typically of the order of several milliseconds. The addition of electrostatic shielding to the relay can reduce the coupling of the electric field from the relay coil to the relay contacts with little attenuation of the needed magnetic force, as is well-known to those trained in relay art.
A voltage ramp immediately before the HBM pulse, anomaly c), is shown at C in FIG. 2. This anomaly is produced by the change in parasitic capacitance between the relay switch contacts as the metal reed armature moves. Because the capacitance between two metal electrodes increases when the distance between the metal electrodes decreases, as the armature contact reed moves away from the normally closed contact toward the normally open contact, the capacitance between the common and normally open contacts increases. Capacitance is measured as the amount of electrical charge stored in a capacitor divided by the voltage across the capacitor; C=Q/V. Current through a capacitor is the change in charge stored with respect to time,
            ⅈ      ⁡              (        t        )              =                            ⅆ          Q                          ⅆ          t                    =                                    ⅆ                          (                              C                ·                V                            )                                            ⅆ            t                          =                  V          ⁢                                    ⅆ              C                                      ⅆ              t                                            ,with the voltage V across the relay switch being approximately constant while the armature moves. The current produced by the relay armature motion is conducted to the DUT by resistor R1 in the prior art circuit of FIG. 1. This current flowing into the DUT can raise the voltage at DUT terminal A even more if the DUT has low capacitance and low leakage, as is common with many IC input terminals. The capacitance between the armature contact and the normally open contact, which is connected to the DUT, continues to increase as the contacts move closer, producing increasing current until the electric field between the armature common contact and the normally open contact reaches the breakdown voltage potential of the inert gas in the glass envelope of the relay. A voltage ramp with an exponentially increasing shape is produced just before the spark/arc discharge occurs that conducts the HBM pulse current from capacitor C1 to the DUT. This pre-pulse voltage ramp can be reduced by selecting a relay switch with small switch contact areas, but that may limit peak currents and shorten the switch's working life.
The secondary or spurious after-pulse(s), anomaly d), is shown at D in FIG. 2, are caused by small discharges occurring after the main discharge of storage capacitor C1, such as when the relay fully closes and makes metal-to-metal contact. In other words, if the capacitor C1 in FIG. 1 is not fully discharged during the HBM pulse from the initial spark discharge, as described above, the remaining energy will be discharged when the armature common connection of S1 makes physical contact to the normally open relay terminal 14. A full discharge of C1 during the HBM pulse does not usually occur. During the spark discharge generated pulse time, the HBM pulse current exponentially decays, with a time constant of approximately 150 nanoseconds. This time constant is controlled by the product of the capacitance of C1 and resistance of R1 plus the DUT impedance. When the current is sufficiently low, the electron avalanche in the high pressure gas that sustains the spark or arc inside the relay switch will not be maintained and the spark will extinguish and the current flow will subside with a small voltage remaining across C1. Should the residual voltage across C1 be large enough to cause another spark discharge through the gas of the relay before the armature completes it motion and closes against the normally open relay terminal, a secondary spurious after-pulse is produced. When the relay switch completes its motion and connects its common terminal to its normally open terminal 14, the residual charge in C1 will be discharged into the DUT. In some relay switches, many spurious pulses can be produced after the main HBM pulse has been generated. Secondary pulses of 10 to 15% of the magnitude of the first HBM pulse are common during operation of the prior art circuit of FIG. 1. What is needed is a circuit that does not generate such multiple secondary pulses.
After an HBM pulse is generated by the spark or arc discharge residual ionization of the gas inside the relay will cause another anomaly, anomaly e) as shown at E in FIG. 2. This ionization typically lasts for hundreds of microseconds, during which time current from the high voltage supply is conducted to the DUT, limited by the impedance of R1 plus the output impedance of the high voltage supply, which is typically 10 megohms in the prior art circuit of FIG. 1. As some DUTs have very high input impedance, leakage of only microamperes can produce a slow ramp to very high voltages, thereby causing gate oxide stress and failures in the ICs under test. What is needed is a means for eliminating this post-pulse current leakage.
HBM testers are implemented to connect and deliver the HBM pulse to any pin on the IC package under test. A requirement of industry standards is also the ability to connect a prescribed number of other IC package pins to a ground return path. The requirements to make a sequence of various connections may be realized by a set of relay switches. The activation and switching of such relay switches can produce noise spikes, anomaly f), as shown at F in FIG. 2. Industry standards specify the inclusion of a series current limiting resistor of value between 10K and 10M ohms to be placed in series with the relay switch S2 of FIG. 1. This prior art prevents a high current discharge of the IC being tested, but it does not prevent relay noise pulses. What is needed is a circuit that isolates the DUT from such relay switch noise spikes.
Practical testers must provide the HBM pulse to various terminals of DUT. Therefore, wiring paths may be constructed to meet specific testing needs and modified by inclusion of relays to configure a pulse delivery path as desired under computer control. It is common in prior art test devices to have several relay switches, or a matrix of relay switches, between R1 and the DUT connections, thus allowing the HBM pulse to be applied to different pins of the DUT. Prior art testers are limited to some extent by the added stray capacitance generated by such a matrix of relay switches. The industry standards require testing with a 500-ohm load to detect excessive stray capacitance between the pulser and the DUT.
The HBM pulse is specified by industry standards to have a rise time from 2 to 10 nanoseconds, followed by an exponentially decay with a time constant of 150 or more nanoseconds. Some ICs have rise time sensitive trigger circuitry to detect such fast pulses and activate ESD protection devices. These ICs can produce different test results when tested with HBM pulses of differing rise times. In prior art HBM test devices, the rise time was determined by parasitic inductances and capacitances in the wiring from pulser to DUT that could not be specified nor changed. This limits the utility of such prior art circuits.
In addition, when an IC or other device being tested is damaged, or “fails”, under the application of an ESD stress pulse, it is often desirable to fully characterize the stress that induced failure. The information provided in prior art ESD HBM testers is only the voltage of the pulse that induced failure. A more complete characterization, valuable to IC design engineers, also includes the current of the pulse applied to the IC as a function of time. From these voltage and current pulse waveforms, which change during the time the pulse is applied to the IC, the actual power delivered to the IC can be calculated. Therefore, a need also exits in the art of ESD test systems for a tester that measures the voltage and current stresses applied to the IC.